View CY7C1373AV25-66AC_1083267.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 512kx36/1mx18 flow-thru sram with nobl? architecture cy7c1371av25 cy7c1373av25 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 6, 2000 25 features pin compatible and functionally equivalent to zbt ? de- vices ? supports 117-mhz bus operations with zero wait states ? data is transferred on every clock internally self-timed output buffer control to eliminate the need to use asynchronous oe registered inputs for flow-through operation byte write capability common i/o architecture single 2.5v power supply fast clock-to-output times ? 7.5 ns (for 117-mhz device) ? 8.5 ns (for 100-mhz device) ? 9.0 ns (for 83-mhz device) ? 10.0 ns (for 66-mhz device) clock enable (cen ) pin to suspend operation synchronous self-timed writes available in 100 tqfp & 119 bga packages burst capability - linear or interleaved burst order functional description the cy7c1371av25 and cy7c1373av25 are 2.5v, 512k by 36 and 1m by 18 synchronous-flow-through burst srams, respectively designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1371av25/cy7c1373av25 is equipped with the advanced no bus latency? (nobl ? ) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically im- proves the throughput of data through the sram, especially in systems that require frequent write/read transitions.the cy7c1371av25/cy7c1373av25 is pin compatible and func- tionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock.the clock input is qualified by the clock enable (cen ) signal, which when deasserted sus- pends operation and extends the previous clock cycle. maxi- mum access delay from the clock rise is 7.5 ns (117-mhz de- vice). write operations are controlled by the byte write selects (bws a,b,c,d for cy7c1371av25 and bws a,b for cy7c1373av25) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. synchronous chip enable (ce 1 , ce 2 , ce 3 on the tqfp, ce 1 on the bga) and an asynchronous output enable (oe ) pro- vide for easy bank selection and output three-state control. in order to avoid bus contention, the output drivers are synchro- nously three-stated during the data portion of a write se- quence. .introduction clk a x cen we bws x ce 1 ce ce 2 oe 256kx36/ memory array logic block diagram dq x data-in reg. q d ce control and write logic 3 adv/ld mode dp x cy7c1371 cy7c1373 ax dqx dpx bws x 512kx18 x = 18:0 x = 19:0 x= a, b, c, d x = a, b x = a, b x = a, b x = a, b, c, d x = a, b, c, d selection guide 117 mhz 100 mhz 83 mhz 66 mhz maximum access time (ns) 7.5 8.5 9.0 10.0 maximum operating current (ma) com?l 250 230 215 180 maximum cmos standby current (ma) 30 30 30 30 shaded areas contain advance information. no bus latency and nobl are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology.
cy7c1371av25 cy7c1373av25 preliminary 2 pin configurations a a a a a 1 a 0 dnu dnu v ss v dd dnu a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss v dd v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bws a ce 3 v dd v ss clk we cen oe nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld nc cy7c1371av25 100-pin tqfp packages a a a a a 1 a 0 dnu dnu v ss v dd a a a a a a a nc nc v ddq v ss nc dpa dqa dqa v ss v ddq dqa dqa v ss v dd v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb vss v dd v ss dqb dqb v ddq v ss dqb dqb dpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bws b bws a ce 3 v dd v ss clk we cen oe nc a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld nc mode cy7c1373av25 bws d mode bws c dqc dqc dqc dqc dpc dqd dqd dpd dqd v ss dpb dqb dqa dqa dqa dqa dpa dqb dqb (512k x 36) (1m x 18) bws b v dd v dd dnu dnu dnu
cy7c1371av25 cy7c1373av25 preliminary 3 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r t u 32m dqa v ddq nc nc nc dqb dqb dqb dqb aa aa 16m v ddq nc a nc v ddq nc v ddq v ddq v ddq nc nc nc 64m a dqb dqb dqb dqb nc nc nc nc tms v dd a a dpb a a adv/ld ancnc v dd a a nc v ss v ss nc nc dpa dqa dqa dqa dqa dqa dqa dqa dnu tdi tdo v ddq tck v ss v ss v ss v ss(1) v ss v ss v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bws b a v ss nc v ss we nc v ddq v dd v ss(1) v dd nc v ss clk nc nc bws a cen v ss nc v ddq v ss nc nc nc a a a a1 a0 v ss nc v dd v ss cy7c1373av25 (1m x 18) - 7 x 17 bga 234 567 1 a b c d e f g h j k l m n p r t u dqa v ddq nc nc dqc dqd dqc dqd aa aa 16m v ddq nc a v ddq v ddq v ddq v ddq nc nc a dqc dqc dqd dqd tms v dd a 64m dpd a a adv/ld ancnc v dd aanc v ss v ss nc dpb dqb dqb dqa dqb dqb dqa dqa dnu tdi tdo v ddq tck v ss v ss v ss v ss(1) v ss v ss v ss v ss mode ce 1v ss oe v ss v ddq bws ca v ss we v ddq v dd v ss(1) v dd v ss clk nc bws a cen v ss v ddq v ss nc nc a a a1 a0 v ss v dd cy7c1371av25 (512k x 36) - 7 x 17 bga dpc dqb a 32m dqc dqb dqc dqc dqc dqb dqb dqa dqa dqa dqa dpa dqd dqd dqd dqd bws d 119-ball bump bga bws b v ss
cy7c1371av25 cy7c1373av25 preliminary 4 pin definitions (100-pin tqfp) x18 pin location x36 pin location name i/o type description 37, 36, 32 ? 35, 44 ? 50, 80 ? 83, 99, 100 37, 36, 32 ? 35, 44 ? 50, 81 ? 83, 99, 100 a0 a1 a input- synchronous address inputs used to select one of the 266,144 address locations. sampled at the rising edge of the clk. 93, 94 93, 94, 95, 96 bws a bws b bws c bws d input- synchronous byte write select inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dqa and dpa, bws b con- trols dqb and dpb, bws c controls dqc and dpc, bws d controls dqd and dpd. 88 88 we input- synchronous write enable input, active low. sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. 85 85 adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address. when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. 89 89 clk input-clock clock input. used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. 98 98 ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. 97 97 ce 2 input- synchronous chip enable 2 input, active high. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. 92 92 ce 3 input- synchronous chip enable 3 input, active low. sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. 86 86 oe input- asynchronous output enable, active low. combined with the synchro- nous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. 87 87 cen input- synchronous clock enable input, active low. when asserted low the clock signal is recognized by the sram. when deassert- ed high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. (a)58, 59, 62, 63, 68, 69, 72 ? 74, (b)8, 9, 12, 13, 18, 19, 22 ? 24 (a)52, 53, 56 ? 59, 62, 63, (b)68, 69, 72 ? 75, 78, 79, (c)2, 3, 6 ? 9, 12, 13, (d)18, 19, 22 ? 25, 28, 29 dqa dqb dqc dqd i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [17:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dqa ? dqd are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe .
cy7c1371av25 cy7c1373av25 preliminary 5 74, 24 51, 80, 1, 30 dpa dpb dpc dpd i/o- synchronous bidirectional data parity i/o lines. functionally, these sig- nals are identical to dq [31:0] . during write sequences, dpa is controlled by bws a, dpb is controlled by bws b, dpc is controlled by bws c, and dpd is controlled by bws d. 31 31 mode input strap pin mode input. selects the burst order of the device. tied high selects the interleaved burst order. pulled low se- lects the linear burst order. mode should not change states during operation. when left floating mode will de- fault high, to an interleaved burst order. 15, 41, 65, 66, 91 15, 41, 65, 66, 91 v dd power supply power supply inputs to the core of the device. 4, 11, 20, 27, 54, 61, 70, 77 4, 11, 20, 27, 54, 61, 70, 77 v ddq i/o power supply power supply for the i/o circuitry. 5, 10, 14, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 5, 10, 14,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss ground ground for the device. should be connected to ground of the system. 64, 84 1-3, 6, 7, 25, 28-30, 51-53, 64, 75, 78, 79 nc - no connects. reserved for address expansion to 512k depths. 38, 39, 42, 43 38, 39, 42, 43 dnu - do not use pins. these pins should be left floating. pin definitions (100-pin tqfp) (continued) x18 pin location x36 pin location name i/o type description
cy7c1371av25 cy7c1373av25 preliminary 6 pin definitions (119 bga) x18 pin location x36 pin location name i/o type description p4, n4, a2, a3, a5, a6, b3, b5, c2, c3, c5, c6, g4, r2, r6, t2, t3, t5, t6 p4, n4, a2, a3, a5, a6, b3, b5, c2, c3, c5 c6, r2, r6, g4, t3, t4, t5 a0 a1 a input- synchronous address inputs used to select one of the 266,144 ad- dress locations. sampled at the rising edge of the clk. l5, g3 l5, g5, g3, l3 bws a bws b bws c bws d input- synchronous byte write select inputs, active low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dqa and dpa, bws b con- trols dqb and dpb, bws c controls dqc and dpc, bws d controls dqd and dpd. h4 h4 we input- synchronous write enable input, active low. sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. b4 b4 adv/ld input- synchronous advance/local input used to advance the on-chip ad- dress counter or load a new address. when high (and cen is asserted low) the internal burst counter is ad- vanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. k4 k4 clk input-clock clock input. used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only rec- ognized if cen is active low. e4 e4 ce 1 input- synchronous chip enable 1 input, active low. sampled on the rising edge of clk. f4 f4 oe input- asynchronous output enable, active low. combined with the synchro- nous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. m4 m4 cen input- synchronous clock enable input, active low. when asserted low the clock signal is recognized by the sram. when deas- serted high the clock signal is masked. since deassert- ing cen does not deselect the device, cen can be used to extend the previous cycle when required. (a)p7, n6, l6, k7, h6, g7, f6, e7 (b)n1, m2, l1, k2, h1, g2, e2, d1 (a)p7, n7, n6, m6, l7, l6, k7, k6 (b)d7, e7, e6, f6, g7, g6, h7, h6 (c)d1, e1, e2, f2, g1, g2, h1, h2 (d)p1, n1, n2, m2, l1, l2, k1, k2 dqa dqb dqc dqd i/o- synchronous bidirectional data i/o lines. as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a [x:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dqa ? dqd are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . d6, p2 p6, d6, d2, p2 dpa dpb dpc dpd i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dqa ? dqd. during write sequenc- es, dpa is controlled by bws a, dpb is controlled by bws b, dpc is controlled by bws c, and dpd is controlled by bws d.
cy7c1371av25 cy7c1373av25 preliminary 7 functional overview the cy7c1371av25/cy7c1373av25 is a synchronous flow-through burst nobl sram designed specifically to eliminate wait states during write-read transitions. all syn- chronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting chip enable(s) (ce 1 , ce 2 , ce 3 on the tqfp, ce 1 on the bga) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write op- eration, depending on the status of the write enable (we ). byte write selects can be used to conduct byte write opera- tions. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry synchronous chip enable (ce 1 , ce 2 , and ce 3 on the tqfp, ce 1 on the bga) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and 4) adv/ld is asserted low. the address presented to the address inputs is latched r3 r3 mode input strap pin mode input. selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode w ill default high, to an interleaved burst order. c4, j2, j4, j6, r4 c4, j2, j4, j6, r4 v dd power supply power supply inputs to the core of the device. a1, a7, f1, f7, j1, j7, m1, m7, u1, u7 a1, a7, f1, f7, j1 j7, m1, m7, u1, u7 v ddq i/o power supply power supply for the i/o circuitry. d3, d5, e3, e5, f3, f5, h3, h5, k3, k5, m3, m5, n3, n5, p3, p5, r5 d3, d5, e3, e5, f3, f5, h3, h5, k3, k5, m3, m5, n3, n5, p3, p5, r5 v ss ground ground for the device. should be connected to ground of the system. j3, j5 j3, j5 v ss(1) these pins have to be tied to a voltage level < v il . they need not be tied to v ss . u5 u5 tdo jtag serial output synchronous serial data-out to the jtag circuit. delivers data on the negative edge of tck. u3 u3 tdi jtag serial input synchronous serial data-in to the jtag circuit. sampled on the rising edge of tck. u2 u2 tms test mode se- lect synchronous this pin controls the test access port state machine. sampled on the rising edge of tck. u4 u4 tck jtag serial output synchronous serial data-out to the jtag circuit. delivers data on the negative edge of tck. a4, t6, t1 a4, t4, t2 16m, 32m 64m - no connects. reserved for address expansion. b1, b2, b7, c1, c7, d2, d4, d7, e1, e6, f2, g1, g5, g6, h2, h7, j3, j5, k1, k6, l2, l3, l4, m6, n2, n7, p1, p6, r1, r7, t7 b2, b7, c7, d4, j3, j5, l4, r1, r7, t1, t7 nc - no connects. u6 u6 dnu - do not use pin. pin definitions (119 bga) (continued) x18 pin location x36 pin location name i/o type description
cy7c1371av25 cy7c1373av25 preliminary 8 into the address register and presented to the memory core and control logic. the control logic determines that a read ac- cess is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another operation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. burst read accesses the cy7c1371av25/cy7c1373av25 has an on-chip burst counter that allows the user the ability to supply a single ad- dress and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented suf- ficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) chip en- able(s) asserted active, and (3) the write signal we is asserted low. the address presented is loaded into the address reg- ister. the write signals are latched into the control logic block. the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dp. on the next clock rise the data presented to dq and dp (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the write operation is controlled by byte write select signals. the cy7c1371av25/ cy7c1373av25 provide byte write capability that is described in the write cycle description table. asserting the write en- able input (we ) with the selected byte write select input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchro- nous self-timed write mechanism has been provided to simpli- fy the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1371av25/cy7c1373av25 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dp inputs. doing so will three-state the output drivers. as a safety precaution, dq and dp are automatically three-stated during the data por- tion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1371av25/cy7c1373av25 has an on-chip burst counter that allows the user the ability to supply a single ad- dress and conduct up to four write operations without reas- serting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is in- cremented. the correct bws a,b,c,d /bws a,b inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
cy7c1371av25 cy7c1373av25 preliminary 9 notes: 1. x = ? don't care, ? 1 = logic high, 0 = logic low, ce stands for all chip enables. ce = 0 stands for all chip enables are active. 2. write is defined by we and bws x . bws x = valid signifies that the desired byte write selects are asserted. see write cycle description table for details. 3. the dq and dp pins are controlled by the current cycle and the oe signal. 4. cen =1 inserts wait states. 5. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 6. oe assumed low. cycle description truth table [1, 2, 3, 4, 5, 6] operation address used ce cen adv/ ld we bws x clk comments deselected external 1 0 0 x x l-h i/os three-state following next rec- ognized clock. suspend - x 1 x x x l-h clock ignored, all operations sus- pended. begin read external 0 0 0 1 x l-h address latched. begin write external 0 0 0 0 valid l-h address latched, data presented two valid clocks later. burst read operation internal x 0 1 x x l-h burst read operation. previous ac- cess was a read operation. ad- dresses incremented internally in conjunction with the state of mode. burst write operation internal x 0 1 x valid l-h burst write operation. previous ac- cess was a write operation. ad- dresses incremented internally in conjunction with the state of mode. bytes written are deter- mined by bws a,b,c,d /bws a,b . interleaved burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
cy7c1371av25 cy7c1373av25 preliminary 10 write cycle description [1] function (cy7c1371av25) we bws dbws cbws bbws a read 1xxxx write ? no bytes written 01111 write byte 0 ? (dqa and dpa) 01110 write byte 1 ? (dqb and dpb) 01101 write bytes 1, 0 01100 write byte 2 ? (dqc and dpc) 01011 write bytes 2, 0 01010 write bytes 2, 1 01001 write bytes 2, 1, 0 01000 write byte 3 ? (dqb and dpd) 00111 write bytes 3, 0 00110 write bytes 3, 1 00101 write bytes 3, 1, 0 00100 write bytes 3, 2 00011 write bytes 3, 2, 0 00010 write bytes 3, 2, 1 00001 write all bytes 00000 function (cy7c1373av25) we bws bbws a read 1 x x write ? no bytes written 0 1 1 write byte 0 ? (dqa and dpa) 0 1 0 write byte 1 ? (dqb and dpc) 0 0 1 write both bytes 0 0 0
cy7c1371av25 cy7c1373av25 preliminary 11 ieee 1149.1 serial boundary scan (jtag) the cy7c1371av25/cy7c1373av25 incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec standard 2.5v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are in- ternally pulled up and may be unconnected. they may alter- nately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the oper- ation of the device. test access port (tap) - test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data in (tdi) the tdi pin is used to serially input information into the regis- ters and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruc- tion that is loaded into the tap instruction register. for infor- mation on loading the instruction register, see the tap con- troller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state dia- gram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuit- ry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block dia- gram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as de- scribed in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the x36 configuration has a xx-bit-long regis- ter, and the x18 configuration has a yy-bit-long register. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register defi- nitions table. tap instruction set eight different instructions are possible with the three-bit in- struction register. all combinations are listed in the instruction code table. three of these instructions are listed as re- served and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller can- not be used to load address, data, or control signals into the sram and cannot preload the input or output buffers. the
cy7c1371av25 cy7c1373av25 preliminary 12 sram does not implement the 1149.1 commands extest or intest or the preload portion of sample / preload; rather it performs a capture of the inputs and output ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap control- ler needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be ex- ecuted whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and there- fore this device is not compliant to the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample / preload instruction has been loaded. there is one difference between the two instructions. unlike the sample / preload instruction, ex- test places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap con- troller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample / preload sample / preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1 compliant. when the sample / preload instructions loaded into the instruction register and the tap controller in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will under- go a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (tcs and tch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample / preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample / preload in- struction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction reg- ister and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advan- tage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cy7c1371av25 cy7c1373av25 preliminary 13 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pau se -i r exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1371av25 cy7c1373av25 preliminary 14 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . x 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [7, 8] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.7 v v oh2 output high voltage i oh = ? 100 a 2.1 v v ol1 output low voltage i ol = 2.0 ma 0.7 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd +0.3 v v il input low voltage ? 0.3 0.7 v i x input load current gnd v i v ddq ? 5 5 a notes: 7. all voltage referenced to ground. 8. overshoot: v ih (ac)< v dd + 1.5v for t< t tcyc /2, undershoot:v il (ac)< 0.5v for t< t tcyc /2, power-up: v ih <2.6v and v dd <2.4v and v ddq <1.4v for t<200 ms.
cy7c1371av25 cy7c1373av25 preliminary 15 tap ac switching characteristics over the operating range [9, 10] parameter description min. max unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 9. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1371av25 cy7c1373av25 preliminary 16 tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi test data-out tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov 50 ? 2.5v 0v all input pulses 1.25v (b)
cy7c1371av25 cy7c1373av25 preliminary 17 identification register definitions instruction field value description revision number (31:28) tbd reserved for version number. device depth (27:23) tbd defines depth of sram. device width (22:18) tbd defines with of the sram. cypress device id (17:12) tbd reserved for future use. cypress jedec id (11:1) tbd allows unique identification of sram vendor. id register presence (0) tbd indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan tbd identification codes instruction code description extest 000 captures the input/output ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register be- tween tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output contents. places the boundary scan register be- tween tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures the input/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1371av25 cy7c1373av25 preliminary 18 boundary scan order bit # signal name bump id bit # signal name bump id 7c1371av25 7c1373av25 7c1371av25 7c1373av25 1 ce 3 ce 3 b6 35 a0 a0 p4 2 bws a bws a l5 36 a a 3 bws b bws b g5 for 1354 37 a a g3 for 1356 38 a a 4 bws c nc g3 39 a a 5 bws d nc l3 40 a a 6 ce2 ce2 b2 41 a a 7 ce 1 ce 1 e4 42 a a 8 a a 43 dpa nc p6 9 a a 44 dqa nc 10 dpc nc d2 45 dqa nc 11 dqc nc 46 dqa nc 12 dqc nc 47 dqa nc 13 dqc nc 48 dqa dqa 14 dqc nc 49 dqa dqa 15 dqc dqb 50 dqa dqa 16 dqc dqb 51 dqa dqa 17 dqc dqb 52 vss vss t7 18 dqc dqb 53 dqb dqa 19 vss vss r5 54 dqb dqa 20 dqd dqb 55 dqb dqa 21 dqd dqb 56 dqb dqa 22 dqd dqb 57 dqb dpa 23 dqd dqb 58 dqb nc 24 dqd dpb 59 dqb nc 25 dqd nc 60 dqb nc 26 dqd nc 61 dpb a 27 dqd nc 62 a a 28 dpd nc p2 63 a a 29 mode mode r3 64 a a g4 30 a a 65 adv/ld adv/ld b4 31 a a 66 oe oe f4 32 a a 67 cen cen m4 33 a a 68 gw gw h4 34 a1 a1 n4 69 clk clk k4
cy7c1371av25 cy7c1373av25 preliminary 19 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +3.6v dc voltage applied to outputs in high z state [12] ....................................? 0.5v to v ddq + 0.5v dc input voltage [12] ................................? 0.5v to v ddq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature [11] v dd /v ddq com ? l 0 c to +70 c 2.5v 5% electrical characteristics over the operating range parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage 2.375 2.625 v v oh output high voltage v dd = min., i oh = ? 1.0 ma [13] 2.0 v v ol output low voltage v dd = min., i ol = 1.0 ma [13] 0.2 v v ih input high voltage 1.7 v dd + 0.3v v v il input low voltage [12] ? 0.3 0.7 v i x input load current gnd v i v ddq ? 5 5 a input current of mode ? 30 30 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 10-ns cycle, 117 mhz 250 ma 12-ns cycle, 100 mhz 230 ma 15-ns cycle, 83mhz 215 ma 15-ns cycle, 66mhz 180 ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in v ih or v in v il f = f max = 1/t cyc 10- ns cycle, 117 mhz 90 ma 12-ns cycle, 100 mhz 80 ma 15-ns cycle, 83mhz 75 ma 15-ns cycle, 66mhz 65 ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 30 ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v, f = f max = 1/t cyc 10- ns cycle, 117 mhz 85 ma 12-ns cycle, 100 mhz 70 ma 15-ns cycle, 83mhz 65 ma 15-ns cycle, 66mhz 55 ma i sb4 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 all speed grades 40 ma shaded areas contain advance information. notes: 11. t a is the case temperature. 12. minimum voltage equals ? 2.0v for pulse durations of less than 20 ns. 13. the load used for v oh and v ol testing is shown in figure (b) of the ac test loads.
cy7c1371av25 cy7c1373av25 preliminary 20 capacitance [14] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = v ddq = 2.5v 4 pf c clk clock input capacitance 4 pf c i/o input/output capacitance 4 pf ac test loads and waveforms output r=1667 ? r=1538 ? 5pf including jig and scope (a) (b) output r l =50 ? z 0 =50 ? v l = 1.25v 2.5v all input pulses [15] 2.5v gnd 90% 10% 90% 10% 2.0 ns 2.0 ns (c) thermal resistance [14] description test conditions symbol tqfp typ. units thermal resistance (junc- tion to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board. ja tbd c/w thermal resistance (junc- tion to case) jc tbd c/w notes: 14. tested initially and after any design or process change that may affect these parameters. 15. input waveform should have a slew rate of > 1 v/ns.
cy7c1371av25 cy7c1373av25 preliminary 21 switching characteristics over the operating range [16] 117 100 83 66 parameter description min. max. min. max. min. max. min. max. unit clock t cyc clock cycle time 8.5 10.0 12.0 15.0 ns f max maximum operating frequency 117 100 83 66 mhz t ch clock high 3.0 3.0 3.0 3.0 ns t cl clock low 3.0 3.0 3.0 3.0 ns output times t cdv data output valid after clk rise 7.5 8.5 9.0 10.0 ns t eov oe low to output valid [14, 19] 3.5 4.0 4.0 4.0 ns t doh data output hold after clk rise 1.5 1.5 1.5 1.5 ns t chz clock to high-z [17, 18, 19] 1.5 5.0 1.5 5.0 1.5 5.0 1.5 5.0 ns t clz clock to low-z [17, 18, 19] 3 3 3 3 ns t eohz oe high to output high-z [17, 18, 19] 4.0 4.0 4.0 4.0 ns t eolz oe low to output low-z [17, 18, 19] 0 0 0 0 ns set-up times t as address set-up before clk rise 2.0 2.0 2.0 2.0 ns t ds data input set-up before clk rise 2.0 2.0 2.0 2.0 ns t cens cen set-up before clk rise 2.0 2.0 2.0 2.0 ns t wes we , bws x set-up before clk rise 2.0 2.0 2.0 2.0 ns t als adv/ld set-up before clk rise 2.0 2.0 2.0 2.0 ns t ces chip select set-up 2.0 2.0 2.0 2.0 ns hold times t ah address hold after clk rise 0.5 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 0.5 0.5 ns t ceh chip select hold after clk rise 0.5 0.5 0.5 0.5 ns shaded areas contain advance information. notes: 16. unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25v, i nput pulse levels of 0 to 2.5v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b) and (c) of ac test loads. 17. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 18. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 19. this parameter is sampled and not 100% tested.
cy7c1371av25 cy7c1373av25 preliminary 22 switching waveforms cen clk address ce we data in/out t cyc t ch t cl t cens t cenh ra1 t ah t as t wes t weh t ces t ceh t cdv q4 q1 = don ? t care = undefined we is the combination of we & bws x (x=a, b, c, d) to define a write cycle (see write cycle description table). out d2 in d5 in out read write deselect write read read read suspend read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh q3 out t chz ce is the combination of ce 1 , ce 2 , and ce 3 . all chip selects need to be active in order to select the device. any chip select can deselect the device. rax stands for read address x, wa stands for device originally deselected write address x, dx stands for data-in x, qx stands for data-out x. q7 out t chz t cens t cenh t doh q6 out read/write/deselect sequence
cy7c1371av25 cy7c1373av25 preliminary 23 switching waveforms (continued) adv/ld clk address ce 1a data in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t cdv q1 = don ? t care = undefined the combination of we & bws x (x=a, b, c, d) define a write cycle (see write cycle description table). out begin read burst read t clz t doh ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t cdv q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bws x t wes t weh we t ws t wh low. during burst writes, byte writes can be conducted by asserting the appropriate bws x input signals. burst order determined by the state of the mode input. cen held low. oe held low. out q3+1
cy7c1371av25 cy7c1373av25 preliminary 24 document #: 38-01005-a switching waveforms (continued) oe three-state i/o ? s oe timing t eohz t eov t eolz ordering information speed (mhz) ordering code package name package type operating range 117 cy7c1371av25-117ac/ cy7c1373av25-117ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack commercial cy7c1371av25-117bgc/ cy7c1373av25-117bgc bg119 7 x 17 bga 100 cy7c1371av25-100ac/ cy7c1373av25-100ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1371av25-100bgc/ cy7c1373av25-100bgc bg119 7 x 17 bga 83 cy7c1371av25-83ac/ cy7c1373av25-83ac a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1371av25-83bgc/ cy7c1373av25-83bgc bg119 7 x 17 bga 66 cy7c1371av25-66ac/ CY7C1373AV25-66AC a101 100-lead 14 x 20 x 1.4 mm thin quad flat pack cy7c1371av25-66bgc/ cy7c1373av25-66bgc bg119 7 x 17 bga shaded areas contain advance information.
cy7c1371av25 cy7c1373av25 preliminary 25 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1371av25 cy7c1373av25 preliminary ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. revision history package diagrams (continued) 119-lead fbga (14 x 22 x 2.4 mm) bg119 51-85115 document title: cy7c1371av25/cy7c1373av25 document number: 38-01005 rev. ecn no. issue date orig. of change description of change ** 3027 4/28/2000 cxv 1. new data sheet *a 3090 6/15/00 cxv 1. correct pin id, pin #43, b2

▲Up To Search▲

Price & Availability of CY7C1373AV25-66AC

	To Download CY7C1373AV25-66AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .